1. Field of the Invention
The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device and a method of manufacturing the same, and in particular relates to an EEPROM (Electrically Erasable and Programmable Read Only Memory) allowing electrical erasing and writing, and more particularly to a so-called flash memory as well as a method of manufacturing the same.
2. Description of the Background Art
An EEPROM, which allows free programming of data and also allows electrical writing and erasing of information, has been known as a kind of nonvolatile semiconductor memory device. The EEPROM has an advantage that both writing and erasing can be electrically performed, but has a disadvantage that high density integration is difficult because two transistors, i.e., a select transistor and a memory cell transistor are required in a memory cell. In view of this, a flash memory which requires one transistor for each memory cell and allows electrical erasing of entire written information charges at a time has been proposed.
FIG. 38 is a block diagram showing a general structure of a flash memory of a NOR type. Referring to FIG. 38, the flash memory includes a memory cell matrix 1100, an X-address decoder 1200, a Y-gate 1300, a Y-address decoder 1400, an address buffer 1500, a write circuit 1600, a sense amplifier 1700, an I/O buffer 1800 and a control logic 1900.
Memory cell matrix 1100 internally has a plurality of memory cell transistors arranged in rows and columns. Memory cell matrix 1100 is connected to X-address decoder 1200 and Y-decoder 1300. X-address decoder 1200 and Y-gate 1300 are operable to select the row and column in memory cell matrix 1100, respectively. Y-gate 1300 is connected to Y-address decoder 1400. Y-address decoder 1400 is operable to provide apply information for selecting the column. X-address decoder 1200 and Y-address decoder 1400 are connected to address buffer 1500. Address buffer 1500 is operable to store temporarily address information.
Y-gate 1300 is connected to write circuit 1600 and sense amplifier 1700. Write circuit 1600 is operable to perform a write operation during input/output of data. Sense amplifier 1700 is operable to determine "0" and "1" from a value of current which flows during the data output. Write circuit 1600 and sense amplifier 1700 each are connected to an I/O buffer 1800. I/O buffer 1800 is operable to store temporarily the input/output data.
Address buffer 1500 and I/O buffer 1800 are connected to a control logic 1900. Control logic 1900 is operable to control an operation of the flash memory. Control logic 1900 performs control based on a chip enable signal /CE, an out-chip enable signal /OE and a program signal. The character "/" in the reference characters such as "/CE" means the inversion or inverted state.
FIG. 39 is an equivalent circuit diagram showing a schematic structure of memory cell matrix 1100 shown in FIG. 38. Referring to FIG. 39, a plurality of word lines WL.sub.1, WL.sub.2, . . . WL.sub.i and a plurality of bit lines BL.sub.1, BL.sub.2, . . . BL.sub.j which extend perpendicularly to the word lines to form a matrix are arranged in memory cell matrix 1100. The plurality of word lines WL.sub.1, WL.sub.2, . . . WL.sub.i are connected to X-address decoder 1200 and extend in the row direction. The plurality of bit lines BL.sub.1, BL.sub.2, . . . BL.sub.j are connected to Y-gate 1300 and extend in the column direction.
Memory transistors Q11, Q12, . . . Qij are arranged at crossings between the word lines and bit lines, respectively. A drain of each memory cell is connected to the corresponding bit line. A control gate of each memory transistor is connected to the corresponding word line. Sources of the memory transistors are connected to corresponding source lines S1, S2, . . . Si. The source lines of the memory transistors belonging to the same row are connected together.
A structure of the memory transistor forming the conventional flash memory will now be described below.
FIG. 40 is a fragmentary plan showing a schematic structure of memory matrix 1100 of the conventional NOR-type flash memory. FIG. 41 is a cross section taken along line D-D' in FIG. 40.
Referring primarily to FIG. 41, a p-type silicon substrate 1001 has a main surface, on which drain diffusion regions 1013 and source diffusion regions 1012 spaced by a predetermined distance are formed to define channel regions 1002 therebetween. A floating gate electrode 1004 is formed on each channel region 1002 with a thin oxide film 1003 of about 100 .ANG. in film thickness therebetween. A control gate electrode 1006 is formed on each floating gate electrode 1004 with an interlayer insulating film 1005 therebetween. Floating gate electrode 1004 and control gate electrode 1006 are made of polycrystalline silicon doped with impurity (which will be referred to as "doped polycrystalline silicon" hereinafter). p-type silicon substrate 1001, floating gate electrodes 1004 and control gate electrodes 1006 are covered with a thermal oxide film 1051. There is also formed a smooth coat film 1008 which is made of, e.g., an oxide film and covers floating gate electrodes 1004 and control gate electrodes 1006.
Smooth coat film 1008 is provided with contact holes each reaching a portion of the surface of source diffusion region 1012. Bit lines 1052 are formed over smooth coat film 1008 and are connected to source diffusion regions 1012 through contact holes 1009, respectively.
Referring primarily to FIG. 40, the plurality of word lines 1006 and the plurality of bit lines 1052 are perpendicular to each other. Word line 1006 is formed integrally with control gate electrode 1006. Floating gate electrode 1004 is formed at the crossing between word line 1006 and bit line 1052, and more specifically is located under control gate electrode 1006. Two floating gate electrodes 1004 which neighbor to each other in the column direction are covered by a common LOCOS (Local Oxidation of Silicon) film 1053.
Referring to FIG. 42, description will be given on a write operation of the NOR-type flash memory utilizing channel hot electrons. A voltage V.sub.D1 from about 4 to about 6 V is applied to drain diffusion region 1013, and a voltage V.sub.G1 from about 10 to about 15 V is applied to control gate electrode 1006. Voltages V.sub.D1 and V.sub.G1 thus applied generate a large number of high energy electrons at the vicinities of drain diffusion region 1013 and oxide film 1003. A part of the electrons are injected into floating gate electrode 1004. When floating gate electrode 1004 accumulates the electrons in this manner, a threshold voltage V.sub.TH of the memory transistor increases. The state in which threshold voltage V.sub.TH exceeds a predetermined value is a written state and is called a state of "0".
Referring to FIG. 43, description will be given on an erasing operation utilizing a F-N (Fowler-Nordheim) tunneling phenomenon. A voltage V.sub.S from about 10 to about 12 V is applied to source diffusion region 1012, control gate electrode 1006 is set to a ground potential, and drain diffusion region 1013 is held at a floating state. Owing to an electric field formed by voltage V.sub.S applied to source diffusion region 1012, the F-N tunneling phenomenon occurs, and thereby the electrons in floating gate electrode 1004 pass through thin oxide film 1003. In this manner, the electrons are extracted from floating gate electrode 1004, so that threshold voltage V.sub.TH of the memory transistor lowers. The state in which the threshold voltage is lower than the predetermined value is the erased state, and is also called a state of "1".
In the read operation, as shown in FIG. 41, a voltage V.sub.G2 of about 5 V is applied to control gate electrode 1006, and a voltage V.sub.D2 from about 1 to about 2 V is applied to drain diffusion region 1013. In this case, the foregoing determination of "1" and "0" is performed based on whether a current flows through the channel region of the memory transistor or not, and in other words, whether the memory transistor is on or off. Thereby, reading of information is performed. The flash memory described above requires the high voltages during the operation as described above. Therefore, it is required to provide a power supply system for high voltages used for erasing independently of a power supply system for a power supply voltage used for ordinary reading in many cases. A flash memory of a DINOR (divided-Bit Line NOR) type suffers from a similar disadvantage.
In order to overcome the above disadvantage, an EEPROM using an injection gate has been proposed in Japanese Patent Laying-Open No. 59-58868 (1984).
FIG. 44 is a cross section of a NOR-type EEPROM using an injection gate disclosed in the above publication. Referring to FIG. 44, a semiconductor substrate 2001 is provided with a source a drain which are diffusion layers of a conductivity type opposite to that of semiconductor substrate 2001. A channel 2004 is formed by ion-implantation of impurity of a conductivity type opposite to that of semiconductor substrate 2001. Channel 2004 is operable to provide continuity between the source and drain of the transistor when no carrier is accumulated in floating gate 2006. Control gate 2008 and floating gate 2006 are capacity-coupled together through a thin insulating film 2007. Injection gate 2008' and floating gate 2006 are capacity-coupled together through a thin insulating film 2013. Oxide film 2007 has a thickness from about 100 to about 500 .ANG., and oxide film 2013 has a thickness of 100 .ANG. or less.
In the erasing operation of the EEPROM thus constructed, a positive voltage is applied to injection gate 2013, whereby electrons tunnel from floating gate 2006 into injection gate 2008', so that the accumulated carriers disappear and the state of "0" is attained.
In the above EEPROM, however, the oxide film under the injection gate is thin. Therefore, the erasing operation can be performed easily, but a leak current is liable to occur at the oxide film. The DINOR-type flash memory suffers from a similar problem.
For overcoming the above problems, the inventors and others have proposed the following EEPROM. FIG. 45 is a cross section of the EEPROM proposed by the inventors and others. Referring to FIG. 45, isolating oxide films 3002 spaced from each other are formed on a silicon substrate 3001. Active regions are formed between isolating oxide films 3002, and gate oxide films 3003 are formed at the active regions, respectively. A floating gate electrode 3004 made of doped polycrystalline silicon is formed on each gate oxide film 3003. Floating gate electrodes 3004 are isolated from each other by isolating oxide films 3002. An interlayer insulating film 3005 formed of a gate oxide film 3005a, a silicon nitride film 3005b and a gate oxide film 3005c is formed on floating gate electrode 3004. An erase electrode 3009 located between neighboring floating gate electrodes 3004 and more specifically above isolating oxide film 3002 is formed on interlayer insulating film 3005 for extracting electrons accumulated in floating gate electrode-3004. An interlayer insulating film 3010 is formed at the surface of erase electrode 3009. Erase electrodes 3009 as well as interlayer insulating films 3005 and 3010 are covered with a control gate electrode 3006. Control gate electrode 3006 is formed of a doped polycrystalline silicon layer 3006a and a silicide layer 3006b made of tungsten silicide or molybdenum silicide.
In this EEPROM, since interlayer insulating film 3005 has a three-layer structure, a leak current is unlikely to occur when it is used as the EEPROM of the NOR type, but such a problem arises that erase electrode 3009 cannot easily extract the electrons accumulated in floating gate electrode 3004. In the case of the DINOR type, erase electrode 3009 cannot easily inject the electrons into floating gate electrode 3004 for erasing. Thus, it becomes difficult to extract and inject electrons for erasing if it is designed to suppress volatilization of data. If it is designed to allow easy extraction and injection of electrons, a leak current is liable to occur and therefore data is liable to volatilize.